1. Field of the Invention
The present invention relates generally to DC-DC converters and more particularly to startup circuitry for controlling power dissipation at converter start up when driving large capacitive loads.
2. Description of Related Art
DC-DC converters are commonly employed to provide varying regulated output voltages using an input power source. In many typical applications, a converter provides a regulated DC output voltage which is larger than the DC input voltage. Such converters are frequently referred to as boost (or step up) converters as opposed to buck (or step down) converters that which provide output voltages smaller than the output. Boost converters include an inductor having one terminal connected to a voltage input with that same terminal also being connected to ground by a first switching transistor. The other inductor terminal is connected to the converter output by way of a second switching transistor. During one phase of a switching cycle the inductor is connected to ground by way of the first switching transistor so that the inductor becomes charged. During a second phase of that switching cycle, the inductor is discharged to a load by way of the second transistor. During that second phase, the voltage drop across the inductor is added to the input voltage to provide a boosted output voltage. The switching duty cycle determines the magnitude of the output voltage. A filter capacitor is present at the output to form an output filter.
During the start up of a boost converter, the output voltage is at or near ground potential. The discharged filter capacitor must be charged so that the voltage across the capacitor reaches the desired regulated output voltage. In some applications, the capacitor is what is commonly referred to as a super capacitor having a capacitance much larger than a typical capacitor. Super capacitor values on the order of 0.05 to 1.9 Farads are not unusual. FIG. 1 shows part of a prior art boost (step up) converter 10 which is configured for startup operation, with the transistor drive circuitry for normal operation not being depicted. During normal converter operation, transistors T1 and T2 are driven in anti-phase. Transistor T1 periodically connects one terminal of the inductor L to ground (while T2 is off) so that the inductor is charged by the input voltage Vin. After inductor charging, transistor T2 is turned on (just after T1 is turned off) so that the charge on the inductor is transferred to the load connected to Vout.
When configured for startup operation, N type transistor T1 is maintained off as indicated by the gate connection to ground. P type transistor T2 is configured as a relatively fixed current source which provides output current Iout to charge capacitor Cs from near ground potential to the normal output voltage Vout. As used herein, the startup phase of boost converter operation begins when the output voltage Vout of the converter begins to increase in value and ends when Vout has nearly reached the fixed input voltage Vin in value. Since the output voltage Vout will be greater than Vin, Vout will continue to increase to its final value, but this action is not considered part of the startup phase.
Transistor T2 is connected relative to another P type transistor T3 to form a current mirror circuit. Since the current through the inductor L will be relatively fixed during start up, the voltage drop across the inductor will be minimal so that the source electrode of T2 is essentially at the same potential as the source electrode of T3, namely Vin. The gate electrodes of T2 and T3 are connected together and to the drain of T3 to complete the mirror circuit. The area of T2 is N time larger than that of T3 so that T2 will conduct N times the current of T3. A fixed current source 11 is connected to draw a current I1 though transistor T3 so that the output current lout will be N times larger than I1. In order to conserve power, N is made relatively large.
The block diagram of FIG. 2 show the FIG. 1 circuitry where block 10 represents the converter and block 12 represents the relatively constant current provided by the current mirror made up of transistors T2 and T3.
In order to reduce the turn on time of regulator 10 it is desirable to maximize the magnitude of lout while not damaging the converter, with T2 being the primary component of concern. Assume for example, that the T2 is part of an integrated circuit having a junction-to-ambient thermal resistance θJA of 70° C./W with this value being largely determined by the circuit packaging. Assume also that there is a specified thermal shutdown temperature of 125° C. at which point temperature sensing circuitry will operate to shut the converter down to prevent damage. The temperature of the junction is given by the following equation:TTSD=TA+(Wmax)(θJA)  Eq. (1)                where                    TTSD is the junction temperature for thermal shutdown (125° C.);            TA is the ambient temperature (40° C.);            Wmax is the maximum power dissipation; and            θJA is thermal resistance (70° C./W).                        
Solving for Wmax, the maximum power dissipation allowed to avoid thermal shutdown is about 1.21 Watts. The worst case voltage drop across pass transistor T2 is Vin−Vout, with Vin typically being +5 volts and Vout being 0 volts at the beginning of start up. The maximum permitted current lout to avoid thermal shutdown is (5 v−0 v)/1.21 W=242 mA. Thus, the current I1 provided by current source 11 is set to 242 mA.
FIG. 3A is a waveform 14 showing the current output lout during start up assuming that the input voltage Vin is +5 volts. The current reaches a peak value of about 240 mA (point 14a) and then drops somewhat as the voltage (Vin-Vout) across T2, which forms the output transistor of the current mirror, drops. As the drain-source voltage of T2 becomes relatively small, transistor T2 no longer acts like a current source that mirrors the current in T3, so the current level begins to drop due to the so-called Early effect. However, as can be seen in FIG. 3B, at the beginning of the turn on process, the power dissipation in T2 is limited to a maximum Wmax of 1.21 watts when the voltage across T2 is at a maximum. Thus, it can be seen that the temperature will be maintained at less than the thermal shut down temperature of TTSD of 125° C. The tradeoff in limiting the current in this manner is that the turn on period required for Vout to reach a final value of +5 volts is over six seconds as can be seen in FIG. 3C by waveform 18. As the final value of +5 volts is approached, the step up converter regulator becomes active to further increase Vout to a predetermined regulated output voltage which will be greater than Vin. As used herein converter startup duration TSU is defined as the amount of time required for the converter output to transition from an output equal to 10% of the converter final startup value of Vin to an output equal to 90% of that final startup value. As can be seen in FIG. 3c the startup duration TSU as defined herein is between 4 and 5 seconds.
There is a need for a converter startup circuit which is capable of safely reducing the turn on time of the converter even when super capacitors are used. As will become apparent from the following Detailed Description of the Invention when read in combination with the drawings, the present invention meets this and other needs.